8088 Assembly Quick Reference

8088 Quick Reference

a compilation of data transfer instructions

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them in memory and registers, and transfer data among the input and output ports.
1 General file transfer instructions.
MOV send word or bytes.
MOVSX 1st sign extension, re-transmission.
MOVZX first zero-expansion,Diesel Jeans, re-transmission.
PUSH the word onto the stack.
POP the word popup up the stack.
PUSHA the AX,Diesel Loose Jeans, CX, DX,Diesel Store, BX, SP, BP, SI, DI turn onto the stack.
; POPA the DI, SI, BP,Diesel Jeans Sale, SP, BX, DX, CX,Diesel Slim Jeans, AX turn up the stack.
PUSHAD the EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI corner onto the pile.
POPAD to EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX turn up the stack.
; BSWAP exchange 32-bit registers in the byte order
XCHG ; exchange of words or bytes (by least one operand is a register, not as an operand segment register)
contrast and exchange operation CMPXCHG digit. (second operand have to accumulator AL / AX / EAX)
XADD the first exchange and then amass. (results in the first operand in)
XLAT word segment look-up table conversion.
─ ─ BX points to a 256 bytes of the table beginning point, AL because the table concordance merits ​​(0-255, namely
; 0-FFH); AL to look-up table to return the results. ([BX + AL] -> AL)
2. input Output wharf transfer instructions.
IN I / O port input (syntax: IN accumulator, port │ DX)
OUT I / O port output (syntax: OUT port │ DX, accumulator)
input and output ports appointed along the way instantly, its range is 0-255; specified along the DX register,
its scope is 0-65535.
3 destination address transfer command.
LEA Load effective address.
Example: LEA DX, string; to offset deposit to the DX. ;
LDS transfer destination pointer, the pointer is loaded into the DS.
Example: LDS SI, string; the segment address: offset address cached apt DS: SI.
LES migrate destination pointer, the arrow is loaded into the ES.
Example: LES DI, string; the segment address: offset address stored to ES: DI.
LFS transfer destination pointer,Diesel Bootcut Jeans, the pointer is loaded into the FS.
Example: LFS DI, string; the segment address: offset address stored to FS: DI.
LGS transfer destination pointer, the pointer is loaded into the GS.
Example: LGS DI, string ;; the segment address: offset deposit to GS: DI.
LSS transfer destination pointer, the pointer is loaded into the SS.
Example: LSS DI, string; the segment address: Offset Address deposit to SS: DI.
4. sign a transfer instruction.
; LAHF flag register transfer, to sign into the AH.
SAHF flag register transfer, the AH is loaded into the flag register.
PUSHF mark stack.
POPF mark stack.
; PUSHD 32 flag onto the stack.
POPD 32 flag stack.
Second, the arithmetic instructions
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ADD addition.
ADC Add with Carry.
INC ; plus 1.
AAA increase of the ASCII code corrections.
DAA Decimal adjust.
SUB subtraction.
SBB Subtract.
DEC minus 1.
; NEC inverted (0-cut of).
CMP ; comparison (two operands for the subtraction, only the modified flag, do not send back the results).
AAS ; subtraction of the ASCII code adjustments.
DAS Decimal adjust. ;
MUL unsigned multiplication.
; IMUL int add.
these two, bring the results behind to the AH and AL (byte operation), or DX and AX (word operation),
AAM multiplication ASCII code adjustments.
DIV unsigned department.
IDIV integer division.
these two, the results echo:
business loopback AL, remainder loopback AH, (byte operation);
or business loopback AX, leftover loopback DX, (word operation) .
AAD division of the ASCII code to adjust.
; CBW bytes into words. (to sign extension of byte in AL to go to the AH)
CWD Convert word to double word. (the word in AX to DX in to sign enhancement)
; CWDE word into a double word. (the sign extension word in AX to EAX go)
; CDQ double word expansion. (in the words of EAX into EDX go sign extension) ;
three plausible instructions
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AND and computing.
OR, or operation.
XOR XOR.
NOT negated.
TEST test (for two operands and operations merely adjust the flag, do not send back the results). ;
SHL Shift Left Logical.
; SAL arithmetic left. (= SHL)
SHR Logical shift right.
SAR arithmetic right. (= SHR)
ROL Rotate Left.
; ROR Rotate Right.
RCL loop through carry left.
RCR Rotate Right through Carry.
above 8 varieties of shift instructions, the shift calculate up to 255 periods.
; shift time, the operation code tin be directly used, such as SHL AX, 1.
; shift> 1, the frequency shift is given by the CL register.
such as MOV CL, 04
; SHL AX, CL
four strings Instruction
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DS: SI source string segment register: source string index.
ES: DI target string segment registers: the target string index
CX repetition counter.
; AL / AX scan values.
; D symbol 0 means the operation ought automatically increment SI and DI; one that ought be auto abatement.
Z flag is used to control the operation of the end of the scan or compare.
; MOVS string transmission.
; (MOVSB ​​transmission character. MOVSW send word. MOVSD transfer double word.)
CMPS string comparison.
(CMPSB more characters. CMPSW more words.)
; SCAS string scanning.
to the AL alternatively AX content compared with the target string to compare the results reflected in the flag.
LODS into the string. ;
the source string element (word or byte) one by one into the AL or AX.
(LODSB transportation character. LODSW ; send word. LODSD transfer double word.)
STOS Save string.
the reverse process is LODS.
; REP if CX / ECX 0 repeat.
REPE / REPZ if ZF = 1 or more are equal, and CX / ECX 0, repeat.
REPNE / REPNZ if ZF = 0 or not equal comparison, and CX / ECX 0 repeat.
REPC When CF = 1 and CX / ECX 0 repeat.
REPNC When CF = 0 and CX / ECX 0 repeat.
five program branches
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1> unconditional branch (L transfer)
JMP unconditional branch
CALL procedure phone
RET / RETF process returns.
2> conditional branch direction (short shift, a distance of -128 to +127)
; (if and only if (SF XOR OF) = 1 时, OP1 interrupt instruction
INT interrupt instruction
INTO overflow interrupt
IRET Interrupt Return
5> processor control instructions
HLT processor suspended until an interrupt or reset before chronic.
WAIT When TEST is high, the piece lead into the CPU wait state.
; ESC switch to the outer processor.
LOCK blocking bus.
NOP No operation.
STC Set carry flag.
CLC remove the carry flag.
CMC carry flag counter. ;
STD Set direction flag.
CLD clear intention flag.
STI to set the interrupt enable bit.
CLI Clear interrupt empower morsel.
VI directive
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DW definition of the word (2 bytes).
PROC definition process.
ENDP end of the process.
SEGMENT definition section.
; ASSUME create segment register addressing.
ENDS end of the block.
END end of the process.