Office Standard 2010 Sale Understanding the VXI VM

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from an engineer Knowing the VXI/VME Interrupt and Signal Acknowledge Cycle
The VME bus specification defines the Priority Interrupt Bus so that a VME device can
asynchronously request support from a controller. This offers a VME/VXI device a means of getting
the controller’s interest at any time.
A VXI/VME bus system has 7 interrupt lines bodily related to all slots from the chassis.
This document addresses interrupts on equally VME and VXI systems.
Interrupt line seven has the greatest priority, and interrupt line one has the lowest priority.
In addition to the genuine interrupt lines, the Priority Interrupt Bus also consists of the
daisy-chained interrupt acknowledge signal and aspects of the Knowledge Transfer Bus
(the knowledge lines,Office Home And Student 2010 Sale, the knowledge acknowledge line, along with the lower 3 address lines).
The table beneath summarizes each and every signal used in the Priority Interrupt Bus and
summarizes the perform of each signal. A gadget that requests services by asserting
one particular of the interrupt lines is known as an interrupter. A purposeful system referred to as
an interrupt handler solutions the interrupt. There may be more than one
interrupt handler within a VXI/VMEbus method. Countrywide Instruments embedded controllers
and exterior MXI bus controllers enable you to configure multiple interrupt handlers
(from a single to 7).
Table I. Priority Interrupt Bus Signals

Signal
Function
IRQ1*-IRQ7*
An interrupter uses this signal to indicate that it is requesting support.
IACK*
An interrupt handler uses this signal to indicate that it has received an interrupt and is ready to receive a status/ID that will tell the handler how to proceed with servicing the interrupt.
IACKIN*/
IACKOUT*
A module receives the IACK* on IACKIN*. It places a status/ID on the bus if the interrupt level being serviced matches the module’s interrupt level and if the system is interrupting. Otherwise, the module passes the signal on using IACKOUT*.
A01-A03
The interrupt handler asserts these lines with the value corresponding to
the interrupt level being serviced.
D00-D31
The interrupter being serviced places the status/ID on these lines once IACK* has been received.
DTACK*
The interrupter uses this signal to indicate that its status/ID is asserted on the data lines.

A more detailed explanation of what happens inside the interrupt cycle is outlined beneath.
A system that requests service by asserting a single from the interrupt lines is called an interrupter. A practical gadget called an interrupt handler companies the interrupt. There may be over one particular interrupt handler within a VXI/VME bus system. However, there can only be 1 interrupt handler per interrupt level in the method. Nationwide Instruments embedded controllers and external MXI bus controllers let you configure multiple interrupt handlers (from one particular to 7).
Therefore, two types of interrupt handler systems are possible:
A single handler program A distributed program
In a very single handler method,Cheap Office 2007, one particular interrupt handler system services all interrupt lines. Within a distributed system, there are two or much more handlers, every single servicing an exclusive subset of your seven interrupt lines. Most methods are single handler methods, where the program controller handles all interrupt lines in the chassis. It is possible for VXI devices to act as programmable interrupt handlers, but this is not very common. The Useful resource manager detects programmable VXI interrupt handlers and uses information stored within the device’s configuration registers to assign the interrupt levels that will be handled by the VXI gadget. Note that VME devices do not define a standard set of configuration registers - you must use Test and Measurement Explorer or VXI Edit/vxitedit to enter any configuration information associated with the VME system.
There are two types of interrupters:
Release On ACKnowledge (ROAK) Release On Register Access (RORA)
Most VXI and VME instruments fall under the ROAK category along with the sequence of events described beneath is only applicable to ROAK devices.
The Sequence of Events During an Interrupt (IACK*) Cycle
After a gadget asserts an interrupt, it waits for a response from the interrupt handler. When the interrupt handler detects that an interrupt line has been asserted, the interrupt handler asserts the IACK* (interrupt acknowledge) signal. It also sets the reduced three tackle lines A01 – A03 to indicate which interrupt line it is trying to acknowledge with the IACK* signal. The IACK* line that the handler drives is related for the IACKIN* pin of slot 0 from the chassis (Slot 1 in VME bus techniques). If the module in the first slot is not asserting the interrupt line being acknowledged,Office Professional 2007 Sale, the module must propagate the IACK* signal to its IACKOUT* pin, which is linked towards the next slot’s IACKIN* pin. The propagation from the IACK* signal from slot to slot continues until the IACK* signal reaches the first module that is interrupting on the line being acknowledged. When the interrupter sees IACK*, it places its status/ID on the data/bus.
The interrupt handler reads the status/ID. Because the interrupt lines are open collector lines, more than one particular device can assert the same interrupt line at the same time. Therefore, the module asserting the interrupt does not propagate the IACK* signal. This action prevents other devices that are interrupting on the same line from finding the IACK* signal and attempting to respond at the same time. After the interrupt handler companies the interrupter, the interrupter releases the line. If other devices are interrupting on the same line, the handler then begins another interrupt acknowledge cycle to services the next interrupter on that line. The following figure illustrates the interrupt acknowledge daisy-chain.
Figure one. Interrupt Acknowledge Daisy-Chain
Note: RORA devices require you to read/write a gadget distinct register in order to complete the interrupt acknowledge cycle.
In this figure, the gadget in slot 4 has asserted an interrupt. The figure shows that if over one device asserts the same interrupt line, the gadget closest to slot 0 (slot one in VME) has the highest priority for interrupt services because it receives the IACK* signal first. The next closest device has the next greatest priority, and so on. It is important to remember that the IACK daisy chain must be related across unoccupied backplane slots,Office 2010 Standard Key, or else interrupts coming from devices to the right of the empty slot will not be acknowledged. Most chassis have jumperless backplanes where this daisy-chain connection happens automatically. However, on older backplanes that are jumpered, jumpers must be utilised to connect the IACK daisy chain across unoccupied slots. On jumpered backplanes, you should also pull the jumpers from the occupied slots so that the IACK daisy-chain is not mistakenly connected through the slot containing the interrupter.

Status/ID Value
The status/ID in most VME systems is an 8-bit value. In VXI systems, the status/ID is either a 16-bit or 32-bit status/ID value. Message-Based devices that have interrupter capability must return at least a 16-bit status/ID with an optional 32-bit value. Currently, 32-bit status/IDs are uncommon. In VME techniques, the status/ID is usually a vector. The processor uses this vector to calculate an address to a position in an interrupt jump table. The entry in that table is the tackle with the start of your interrupt services routine.
Therefore, when the processor handles the interrupt and receives the status/ID, it jumps directly to the beginning of the interrupt support routine and executes the interrupt services routine code. The method integrator installs the interrupt support routine at the memory location that the jump table specifies.
In VXI systems (and all National Instruments VXI/VME Controllers),Office Standard 2010 Sale, the status/ID is no longer a
vector. It is de-coupled from the processor operation. After the interrupt handler receives the
status/ID, controller software invokes the appropriate support subroutine and passes the
status/ID value towards the subroutine.
The general format of your status/ID for a Register-Based VXI device is shown
inside the following table.
Table II. General Status/ID Format for VXI Bus Devices

Bits
31-16
15-8
7-0
Contents
Device-Dependent
Cause/Status
(Device-Dependent)
Logical Address
of Interrupter
For Message-Based VXI devices, there is a further definition of the status/ID format. The status/ID can take on either a Response format or an Event format. Under the Event Format, bit 15 of the status/ID must be set. The values of status/ID bits 8 through 14 define the Event condition. The VXI bus specification currently defines these bits for 3 distinct events. It also defines a syntax for defining your own events. The events defined from the VXI bus specification and their corresponding values for status/ID bits 8 through 15 are listed beneath.
No Cause Given (0xFF) - This event is sent by a Register-Based gadget that has only a single reason to signal its Commander. Usually, this event is issued when an operation completes.
Request True (0xFD) — This event is sent by a gadget when the gadget requires services.
Request False (0xFC) — This event is sent by the gadget when the gadget no longer requires services. The VXI bus specification also defines a syntax for sending user-defined
events. This format specifies that bit 15 must be one and bit 14 must be 0. Bits 8 – 13 can then be employed to specify a user-defined event, as shown in the following table.

Table III. Message-Based System Status/ID—User-Defined Event Format

Bits
31-16
15
14
13-8
7-0
Contents
Device-Dependent
1
0
User-Defined Event
Logical Address
of Interrupter
Except for defining the reduce 8 bits of the status/ID value to be the logical deal with of the interrupter, the VXI bus specification defines only a few distinct values from the status/ID. Usually, when you are working with a gadget capable of producing interrupts, you need to refer to the documentation accompanying the device to see what meaning, if any, the other bits with the status/ID have. Often, you control the conditions under which the interrupt is generated, as well as the actual status/ID is not important because you will know in advance why the device is sending interrupts.

Signals
Instead of asserting an interrupt line, some devices can request service by producing a signal. "Signal" in this context is not an electrical signal (such as the backplane signals discussed earlier from the course), but rather a write of a 16-bit value to your signal register of another system. The signal register is simply a VXI configuration register that has a value written to it by another system capable of taking control of your bus. Not all devices implement a signal register. The term signal originates from its use in UNIX, where a signal is a means of inter-process communication. To use signals, the following two conditions must apply:
The signaling gadget must be able to take control of your VXI bus The device to which the signal is being sent must implement a signal register.
The signaling device uses the Data Transfer Bus to write a 16-bit value towards the signal register, which is located at offset 8 within the configuration registers for the gadget being signaled. The 16-bit value has exactly the same format as the 16-bit status/ID.
The procedure for handling a signal through software is the same as for an interrupt. The processes discussed above for signals and also the interrupt cycle happen completely on the hardware level. These processes are transparent to a user’s application. When a controller senses an interrupt or sees that its signal register has been written to, the controller generates a local processor interrupt that lets the software driver know the event has occurred.